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core_cmFunc.h
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1/**************************************************************************/
10/* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#ifndef __CORE_CMFUNC_H
39#define __CORE_CMFUNC_H
40
41
42/* ########################### Core Function Access ########################### */
47
48#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49/* ARM armcc specific functions */
50
51#if (__ARMCC_VERSION < 400677)
52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
53#endif
54
55/* intrinsic void __enable_irq(); */
56/* intrinsic void __disable_irq(); */
57
64__STATIC_INLINE uint32_t __get_CONTROL(void)
65{
66 register uint32_t __regControl __ASM("control");
67 return(__regControl);
68}
69
70
77__STATIC_INLINE void __set_CONTROL(uint32_t control)
78{
79 register uint32_t __regControl __ASM("control");
80 __regControl = control;
81}
82
83
90__STATIC_INLINE uint32_t __get_IPSR(void)
91{
92 register uint32_t __regIPSR __ASM("ipsr");
93 return(__regIPSR);
94}
95
96
103__STATIC_INLINE uint32_t __get_APSR(void)
104{
105 register uint32_t __regAPSR __ASM("apsr");
106 return(__regAPSR);
107}
108
109
116__STATIC_INLINE uint32_t __get_xPSR(void)
117{
118 register uint32_t __regXPSR __ASM("xpsr");
119 return(__regXPSR);
120}
121
122
129__STATIC_INLINE uint32_t __get_PSP(void)
130{
131 register uint32_t __regProcessStackPointer __ASM("psp");
132 return(__regProcessStackPointer);
133}
134
135
142__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
143{
144 register uint32_t __regProcessStackPointer __ASM("psp");
145 __regProcessStackPointer = topOfProcStack;
146}
147
148
155__STATIC_INLINE uint32_t __get_MSP(void)
156{
157 register uint32_t __regMainStackPointer __ASM("msp");
158 return(__regMainStackPointer);
159}
160
161
168__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
169{
170 register uint32_t __regMainStackPointer __ASM("msp");
171 __regMainStackPointer = topOfMainStack;
172}
173
174
181__STATIC_INLINE uint32_t __get_PRIMASK(void)
182{
183 register uint32_t __regPriMask __ASM("primask");
184 return(__regPriMask);
185}
186
187
194__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
195{
196 register uint32_t __regPriMask __ASM("primask");
197 __regPriMask = (priMask);
198}
199
200
201#if (__CORTEX_M >= 0x03)
202
208#define __enable_fault_irq __enable_fiq
209
210
216#define __disable_fault_irq __disable_fiq
217
218
225__STATIC_INLINE uint32_t __get_BASEPRI(void)
226{
227 register uint32_t __regBasePri __ASM("basepri");
228 return(__regBasePri);
229}
230
231
238__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
239{
240 register uint32_t __regBasePri __ASM("basepri");
241 __regBasePri = (basePri & 0xff);
242}
243
244
251__STATIC_INLINE uint32_t __get_FAULTMASK(void)
252{
253 register uint32_t __regFaultMask __ASM("faultmask");
254 return(__regFaultMask);
255}
256
257
264__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
265{
266 register uint32_t __regFaultMask __ASM("faultmask");
267 __regFaultMask = (faultMask & (uint32_t)1);
268}
269
270#endif /* (__CORTEX_M >= 0x03) */
271
272
273#if (__CORTEX_M == 0x04)
274
281__STATIC_INLINE uint32_t __get_FPSCR(void)
282{
283#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
284 register uint32_t __regfpscr __ASM("fpscr");
285 return(__regfpscr);
286#else
287 return(0);
288#endif
289}
290
291
298__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
299{
300#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
301 register uint32_t __regfpscr __ASM("fpscr");
302 __regfpscr = (fpscr);
303#endif
304}
305
306#endif /* (__CORTEX_M == 0x04) */
307
308
309#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
310/* IAR iccarm specific functions */
311
312#include <cmsis_iar.h>
313
314
315#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
316/* TI CCS specific functions */
317
318#include <cmsis_ccs.h>
319
320
321#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
322/* GNU gcc specific functions */
323
329__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
330{
331 __ASM volatile ("cpsie i" : : : "memory");
332}
333
334
340__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
341{
342 __ASM volatile ("cpsid i" : : : "memory");
343}
344
345
352__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
353{
354 uint32_t result;
355
356 __ASM volatile ("MRS %0, control" : "=r" (result) );
357 return(result);
358}
359
360
367__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
368{
369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
370}
371
372
379__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
380{
381 uint32_t result;
382
383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
384 return(result);
385}
386
387
394__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
395{
396 uint32_t result;
397
398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
399 return(result);
400}
401
402
409__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
410{
411 uint32_t result;
412
413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
414 return(result);
415}
416
417
424__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
425{
426 register uint32_t result;
427
428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
429 return(result);
430}
431
432
439__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
440{
441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
442}
443
444
451__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
452{
453 register uint32_t result;
454
455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
456 return(result);
457}
458
459
466__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
467{
468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
469}
470
471
478__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
479{
480 uint32_t result;
481
482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
483 return(result);
484}
485
486
493__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
494{
495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
496}
497
498
499#if (__CORTEX_M >= 0x03)
500
506__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
507{
508 __ASM volatile ("cpsie f" : : : "memory");
509}
510
511
517__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
518{
519 __ASM volatile ("cpsid f" : : : "memory");
520}
521
522
529__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
530{
531 uint32_t result;
532
533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
534 return(result);
535}
536
537
544__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
545{
546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
547}
548
549
556__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
557{
558 uint32_t result;
559
560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
561 return(result);
562}
563
564
571__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
572{
573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
574}
575
576#endif /* (__CORTEX_M >= 0x03) */
577
578
579#if (__CORTEX_M == 0x04)
580
587__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
588{
589#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
590 uint32_t result;
591
592 /* Empty asm statement works as a scheduling barrier */
593 __ASM volatile ("");
594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
595 __ASM volatile ("");
596 return(result);
597#else
598 return(0);
599#endif
600}
601
602
609__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
610{
611#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
612 /* Empty asm statement works as a scheduling barrier */
613 __ASM volatile ("");
614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
615 __ASM volatile ("");
616#endif
617}
618
619#endif /* (__CORTEX_M == 0x04) */
620
621
622#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
623/* TASKING carm specific functions */
624
625/*
626 * The CMSIS functions have been implemented as intrinsics in the compiler.
627 * Please use "carm -?i" to get an up to date list of all instrinsics,
628 * Including the CMSIS ones.
629 */
630
631#endif
632
634
635
636#endif /* __CORE_CMFUNC_H */